SUSS MicroTec and Fraunhofer IST jointly launch new technologies for selective surface treatment

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, and the Fraunhofer IST Fraunhofer Institute for Layers and Surface Technology have announced the release of a new technology called SEL ECT for lithography and bonding. In alignment, a portion of the wafer body can be selectively activated by plasma. Regional plasma activation prior to the wafer start-up process can change traditional process steps and effectively reduce the total cost per wafer. Selective plasma activation can be used in a variety of MEMS, optical, and solar manufacturing processes to directly perform wafer bonding or surface characterization for micromirror arrays, microvalves, sensors, and microchannels. SELECT is an optional upgrade to the SUSS MicroTec MA/BA8 Gen3.

Fraunhofer IST is applying for a patent for this SELECT technology. This technology selectively changes the molecular-scale surface structure using plasma in an atmospheric pressure environment. Conventional surface treatments cannot select areas and can only handle the entire wafer, which can affect or even damage the functionality of the microstructure or electronics. Selective processing protects sensitive areas and only activates specific areas of the wafer. The regional plasma treatment can handle wafers that are flat or have a three-dimensional configuration of the surface, and can activate only the cavity or only the raised structure.

“Using regional plasma processing in the wafer bonding process, the post-bonding annealing temperature can be reduced from 1000°C to 200°C, effectively protecting the vulnerable chips. This technology has greatly expanded the wafer. "The process window of the bond bonding," said Professor Günter Br?uer, head of Fraunhofer IST. "SUSS MicroTec's SELECT component, used in the semiconductor industry's chip process, will provide breakthroughs in wafer bonding and other wafer processes. A new way of crafting."

“Using wafer selection area processing will effectively reduce chip production costs and increase production capacity,” explains Frank Averdung, president and CEO of SUSS MicroTec. “The new SELECT technology is likely to completely change the cost model of many applications. This creates an attractive opportunity for our new manual lithography users."

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