Detailed explanation of CAN bus signal transmission bit timing and bit synchronization

One of the differences between the CAN protocol and other fieldbus protocols is that it uses synchronous data transfer instead of asynchronous transfer (for characters). This means that transmission performance is more effectively played, but on the other hand, this requires a more complex bit synchronization method.

Bit synchronization in character-oriented protocols is simple to implement and is synchronized when the start bit of each character is accepted. However, in the isochronous transfer protocol, there is only one start bit at the beginning of a frame. This is usually not enough to keep the receiver's bit samples and transmitters in sync. In order for the receiver to correctly sample the received bit stream at the end of the frame, the receiver is required to continuously resynchronize. Resynchronization means that each valid signal edge in the bitstream can detect the clock period of the received signal. During the maximum time period between signal edges, the maximum possible time difference between transmitting and receiving the oscillator must be compensated for by sufficient idle time ("phase buffer segment") before and after the nominal sample point within one bit interval.

Since the CAN protocol uses non-destructive bit bus arbitration and explicit acknowledge bits, the signal must be transmitted from the transmitter to the receiver and back to the receiver in one bit time. Therefore, in addition to the time reserved for synchronization, a time period ("Transmission Delay Segment") is required to compensate for signal transmissions on the bus and internal signal delays for the transmitting and receiving nodes.

The length of a bit interval period is defined as a multiple of a basic time unit (time share), depending on the oscillator period. The basic time unit tq is a basic unit representing the time resolution of the synchronization mechanism and is introduced into the bit time because of the synchronization segment. The sync segment is the portion of the edge of the CAN signal level that will be generated during bit time. The distance between the edge generated after the sync segment and the sync segment is called the "phase error e" of the edge.

The transmission delay segment provides the necessary time to handle the maximum signal transmission delay in the network. This time period must be twice the sum of the maximum signal transmission delay time between the two nodes plus the internal delay time of the transmitting and receiving nodes.

There are two types of synchronization that need to be distinguished: "hard sync" at the beginning of the frame and "resync" in the middle of the frame. After hard synchronization, the bit time is restarted at the end of the sync segment regardless of the phase error. This hard synchronization forces the edge of the hard sync to extend into the sync segment of the restarted bit time. Resynchronization causes the bit time to be shortened or lengthened, causing the sampling points to shift.

The idle time is reserved for the shift of the actual sample point during resynchronization by the phase buffer segment before and after the nominal sample point. Synchronization only occurs on the edge where the recessive bit transitions to the dominant bit level. The edge can be detected by sampling the actual level of the bus for each amount of time and comparing it to the bus level of the previous sample point. If an edge is detected within the sync segment, then the edge can be synchronized, otherwise the distance between the edge of the signal and the end of the sync segment is the edge phase error (calculated in terms of time). If the edge occurs before the sync segment, the phase error is negative, otherwise it is positive.

If the phase error is positive, phase buffer segment 1 will be extended. The maximum number of phase buffer segments shortened or extended ("synchronous jump width", SJW) is limited each time it is resynchronized, and it can be programmed to a value between 1 and Min{4, Phase_Seg1}.

When the value of the signal edge phase error is less than or equal to the programmed value of SJW. The values ​​for hard sync and resynchronization will be the same. If the number of phase errors is greater than SJW, resynchronization will not fully compensate for the phase error, so the error (phase error - SJW) still exists.

Only one synchronization is allowed between the two sample points. The resynchronization maintains the minimum distance between the edge and the sample point, making the bus level stable and filtering out the peak less than the sum of the transmission segment and phase segment 1 time.

Different segments within a bit time can be programmed according to the following limits:

Sync_Seg: 1 time share

Prop_Seg1:1...8 or more time share

Phase_Seg1:1...8 or more time share

Phase_Seg2: Max{Phase_Seg1, information processing time}

Baud rate prescaler: 1...32

SJW: 1...4, but not greater than Min{4, Phase_Seg1}

During synchronization, Phase_Seg1 can be longer than the programmed nominal time and Phase_Seg2 can be shorter than the nominal time.

The "data processing time" starts after the sampling point, which is the time (for example, data bit, CRC bit, padding bit, error flag, or idle) used to determine the bit level to be subsequently transmitted. This time cannot be greater than 2 time quantities. Its length is the lower limit of the Phase_Seg2 programmed value. Phase_Seg2 can be less than the data processing time during synchronization, which does not affect the timing of the bus.

The time share value for each bit time must be set to a range of 8 to 25.

If the transmitter's oscillator is slower than the receiver (a), the edge of the signal used for synchronization will delay arriving at the receiver. The receiver can be compensated by the shift of the sampling point. The maximum cumulative "delay" (edge ​​phase error) that can be compensated is determined by the time that phase segment 1 is reserved. During resynchronization, if the value of the phase error is less than or equal to SJW, the sample point is shifted according to the edge phase error e that occurs, and thus the position of the sample point associated with the current bit position is restored.

When the transmitter's oscillator is faster than the receiver (b), the signal edge arrives earlier than the receiver expects, so the next bit interval must be started earlier. This is achieved by shortening the phase buffer segment 2. In this case, the sync segment is omitted, so after resynchronization, the distance from the signal edge to the sample point is equal to the distance between the sync segment and the sample point (if no edge is detected). In the first example, the phase error value of the "advance" edge is less than SJW, so full compensation can be achieved.

The phase buffer segment is only temporarily changed, and if no phase error is detected in the next bit time, they will return to the nominal value. The receiver expects the edge to appear in the sync segment.

The following is the rule applied to bit synchronization [ISO99-1]:

There is only one synchronization between two sampling points in one bit time.

Synchronization from recessive to dominant signal edges can only be used when the signal level detected at the previous sample point is different from the signal level at the next sample point. A short interfering pulse is not working.

As soon as a recessive to dominant signal edge occurs while the bus is idle, a "hard sync" (start of the new bit interval) is performed.

A recessive to dominant signal edge in the interframe space (except for the first bit of the intermittent field) causes a hard synchronization to be performed.

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