How does the frequency hopping controller work?

This content describes the working principle of the frequency hopping controller, and explains in detail how the transmission path and the receiving channel work.

First, the working principle of the frequency hopping controller transmission path is introduced.

(1) The digitized transmission signal is added to the serialization and output registers of the FC, and the FC organizes the transmission data into a 16-bit group. When the two data bytes are ready, the FC signals the CPU, the CPU reads the two bytes, and stores them in the RAM portion of the FIFO register. The starting point of the FIFO controller is synchronized with the starting point of the frequency hopping period (represented by the signal HOP).

(2) The FC also includes an 8-bit in-line serial register. The data sent to the transceiver module is taken out of this register. During the transmission of the synchronization sequence and during the frequency conversion, data from the serial-to-out register of the FC is accumulated in the RAM portion as the FIFO.

(3) The data byte of the FC incorporated into the register is shifted out by the signal FOUT-STOPPED (frequency is 18.3 kHz). The rate of removal (18.3 kHz) is higher than the rate at which data is loaded into the FC (16 kHz). The difference between the two data rates allows the CPU to insert the synchronization data into the transmit data stream and stop transmitting data during the frequency translation.

(4) The data removed by the FC is sent to the radio frequency audio interface RAI module. The RAI filters the transmitted signal and adds the resulting signal TXBBR to the transceiver module system connector.

The working principle of the frequency hopping controller receiving path will be described below.

(1) The RAI passes the received signal RXBBR to the bit synchronizer BIS, the correlator COR, and is applied to the FC via a linear equalizer.

(2) COR compares the received data with the reference sequence provided by the CPU bit by bit. When the consistent bit number is greater than the threshold provided by the CPU, COR gives the relevant pulse.

(3) The positive correlation pulse and the negative correlation pulse are applied to the SYTD microelectronic module located in the RC module. The SYTD monitors the positive correlation pulse to detect the synchronization sequence. When a synchronization sequence is detected, SYTD generates signal S4. The occurrence of S4 is controlled by a window signal W2.

(4) The bit synchronizer BIS synchronizes the reception clock FOUT of the frequency hopping controller with the actual clock rate of the received data. A window signal W1 blocks the FOUT signal during the 4ms pilot interval of the transceiver module and when receiving synchronous data.

(5) The FC sends the received data to the FIFO register and then from the FIFO register to the RAI or DM. In the receive mode, the FC operates in the opposite way to the transmit mode, ie, the data is injected into the controller at a rate of 18.3 kHz and read out from the controller at a rate of 16 kHz.

(6) The serial data appearing at the FC output is added to the DM. The DM converts the data into an analog signal and sends it to the AI.

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