Board from entry to proficiency (5): software and hardware co-design

The biggest advantage of Zynq is that it has both software, hardware, and IO programmable, namely All Programmable. In the process of designing Zynq, it is also necessary to establish a kind of consciousness, which is to liberate from the original pure software thinking (or pure hardware thinking) and turn to the development method of software and hardware collaborative design.

Software design, that is, ARM-based software development, we have already done examples in the third section, basically through a hardware address mapping register and the corresponding hardware to interact, such hardware including ARM peripherals such as GPIO, EMIO, SPI , TImer, etc., also includes the PL mounted on the AXI bus. In addition, the software has to deal with high-level tasks such as operating systems and networks.

Hardware design, that is, FPGA-based logic development, mainly by instantiating some off-the-shelf IP, using the state machine to implement its own logic functions, and then implementing AXI interface to communicate with ARM.

Designing a combination of hardware and software requires an AXI bus. We have repeatedly stressed the importance of AXI, it can be said that it determines the success or failure of software and hardware co-design.

There are also a lot of web tutorials about Zynq. Like lazy rabbits, when I started to learn Zynq, I followed the tutorial step by step. This tutorial will not repeat these steps, but will help beginners to build a framework, and the rest is to fill in the specific content by checking the documentation and experimenting.

We roughly divide the framework developed by Zynq:
The first is the demand analysis, to determine what to do; after the task is subdivided, generally can see which is suitable for implementation on the FPGA, separately proposed; the rest are using PS. Then select the communication interface, the physical link selects GP or HP or ACP, and the protocol selects AXI-Lite, AXI-FIFO or AXI-Stream. After the division is completed, the logic engineer and the ARM engineer will separate from each other and implement according to their respective tasks.

Logic engineers need to focus on IP design, integrate functionality into a single user IP, and leave communication interfaces to communicate with AXI.

ARM engineers build ARM bare metal software engineering or embedded Linux based projects according to requirements. The former has a short development cycle, while the latter has strong functions but needs to do a lot of preparation for Linux (boot, kernel, file system, driver, graphical interface development). Wait). Although the development based on embedded Linux seems to be "cool", we must grasp the scale, and can barely use the operating system with bare metal, otherwise it will only hurt people.

After the completion of the respective development work, enter the joint adjustment, ARM reads and writes the PL mapping register to check whether the corresponding function is normal. If it is not normal, it needs to be reworked and modified repeatedly until the problem is solved.


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